In general, a time processor unit (TPU) is an intelligent semi-autonomous microcontroller that is designed for timing control. The TPU operates simultaneously with an integrated central processing unit (CPU) and schedules tasks, processes microcode read only memory (ROM) instructions, accesses data shared with the CPU and performs input and output (I/O) functions. For example, TPUs have been included with various microprocessors within the Motorola 68xxx family. With reference to FIG. 1, an exemplary TPU 100 is shown coupled to a CPU 50, which is coupled to a memory subsystem 52. The TPU 100 can be viewed as a special purpose microcontroller that performs a programmable series of two operations, i.e., match and capture. The occurrence of a match or capture is known as an event and a programmed series of events is called a function. In general, TPU functions replace software functions that would have required the CPU 50 to service an interrupt.
With reference to the TPUs incorporated within a Motorola MC68336/376, an A mask set and a G mask set provide various functions. The A mask set provides for the following functions: discrete I/O; input capture/input transition counter; output compare; pulse width modulation; synchronized pulse width modulation; period measurement with additional transition detect; period measurement with missing transition detect; position-synchronized pulse generator; stepper motor; period/pulse width accumulator; and quadrature decode. The G mask set allows for the following functions: table stepper motor; new input capture/transition counter; queued output match; programmable time accumulator; multichannel pulse width modulation; fast quadrature decode; universal asynchronous receiver/transmitter; brushless motor communication; frequency measurement; and Hall effect decode.
When the TPU 100 is a Motorola MC68336/376, the TPU 100 includes two 16-bit reference time bases 110A and 110B, sixteen independent timer channels 112, a task scheduler 106, a microengine 108 and a host interface 104. A dual-ported parameter random access memory (RAM) 104A is included within the host interface 104 and is used to pass parameters between the TPU 100 and the CPU 50. Two 16-bit counters (TCR1) 110A and (TCR2) 110B provide reference time bases for output compare and input capture events.
Prescalers for the time bases are controlled by the CPU 50, via bit fields in the TPU module configuration register. Timer count registers TCR1 and TCR2 provide access to the current counter values. The timer count registers TCR1 and TCR2 can be read by TPU microcode, but are not directly available to the CPU. The TCR1 clock is derived from the system clock and the TCR2 clock can be derived from the system clock or from an external clock input, via a T2CLK pin.
As mentioned, the TPU has sixteen independent channels 112, each of which are connected to a pin of the CPU 50. In general, the channels 112 have identical hardware and each channel 112 includes an event register and pin control logic. The event register contains a 16-bit capture register, a 16-bit compare/match register and a 16-bit greater-than-or-equal-to comparator. The direction of each pin, either input or output, is determined by the microengine 108. Each channel can either use the same time base for match and capture or use one time base for match and the other for capture.
When a service request is received, the scheduler 106 determines which of the channels 112 is serviced by the microengine 108. The channels 112 can request service for one of four reasons: for host service;                for a link to another channel; for a match event; or for a capture event. The host system assigns each active channel one of three priorities; high, middle or low. When multiple service requests are received simultaneously, a priority scheduling mechanism grants service based on channel number and assigned priority.        
The microengine 108 includes a control store unit 108A and an execution unit 108B. A control store ROM (not separately shown) holds microcode for each factory-masked time function. When assigned to a channel by the scheduler 106, the execution unit 108B executes microcode for a function assigned to that channel by the CPU 50. The microcode can also be executed from a TPU RAM module instead of the control store 108A. The TPU RAM module allows emulation and development of custom TPU microcode without the generation of a microcode ROM mask. The host interface 104 includes registers that allow for communication between the CPU 50 and the TPU 100 before and during execution of a time function. The registers are accessible from the intermodule bus (IMB) 102 through a bus interface unit. A parameter RAM 104A is located within the host interface 104 and typically occupies 256 bytes at the top of the system address map.
Channel parameters are organized as 128 16-bit words, which can all be accessed by all of the channels. The CPU 50 specifies function parameters by writing to an appropriate RAM 104A address. The TPU reads the RAM 104A to determine the channel operation and can also store information to be read by the CPU 50 in the parameter RAM 104A. The TPU functions are related to one of two 16-bit time bases and functions are synthesized by combining sequences of match events and capture events. The TPU 100 can determine precisely when a match or a capture event occurs and respond rapidly as the primitives are implemented in hardware. An event register for each of the channels 112 provides for simultaneity of match/capture event occurrences on all of the channels 112.
When a match or input capture event requiring service occurs, the affected one of the channels 112 generates a service request to the scheduler 106. The scheduler 106 determines the priority of the request and assigns one of the channels 112 to the microengine 108 at a first available time. The microengine 108 performs the function defined by the content of the control store 108A or emulation RAM using parameters from the parameter RAM 104A located within the host interface 104. Match and capture events are handled by independent channel hardware, which provides for event accuracy of one time base clock period, irrespective of the number of the channels 112 that are active. Inner-channel communication within the TPU 100 can be accomplished by issuing a link service request to another channel, by controlling another channel directly or by accessing assigned memory in the parameter RAM 104A of another channel.
As is briefly mentioned above, the TPU 100 includes limited sized bit timers, e.g., 16-bits, which may, depending upon the application, not include enough bits for performing a desired time function. For example, at 1 microsecond, a 16-bit timer would overflow at 65.5 milliseconds. In practice, to create an extended range timer has required the TPU 100 to wake-up when the 16-bit timer rolls over from FFFFh to 0000h to increment an extra byte or bytes. In order to perform this wake-up, one of the TPU channels 112 has been utilized to schedule the event. Unfortunately, using one of the channels in order to create an extended bit timer has reduced the number of the channels 112 that are available for other functions and, in certain situations, can result in a TPU being unable to perform another function, due to the limited number of TPU channels. In this particular situation, a designer may be required to implement additional TPUs, due to the utilization of channels to implement an extended range timer.
What is needed is a technique that allows a TPU to perform extended range timer functions without utilizing one of the channels of the TPU to perform the function.